2024COS1 60616 PARALLEL TO SERIAL CONVERTER CODE
5%).Ĩb/10b SerDes maps each data byte to a 10-bit code before serializing the data. As the clock is explicitly embedded and can be recovered from the bit stream, the serializer (transmitter) clock jitter tolerance is relaxed to 80–120 ps rms, while the reference clock disparity at the deserializer can be ±50,000 ppm (i.e. One cycle of clock signal is transmitted first, followed by the data bit stream this creates a periodic rising edge at the start of the data bit stream. The clock jitter tolerance at the serializer is 5–10 ps rms.Īn embedded clock SerDes serializes data and clock into a single stream. The serialized stream is sent along with a reference clock. Parallel clock SerDes is normally used to serialize a parallel bus input along with data address & control signals. The purpose of this encoding/decoding is typically to place at least statistical bounds on the rate of signal transitions to allow for easier clock recovery in the receiver, to provide framing, and to provide DC balance. Some types of SerDes include encoding/decoding blocks. One register is used to clock in the serial stream, and the other is used to hold the data for the slower, parallel side. Implementations typically have two registers connected as a double buffer. The SIPO block then divides the incoming clock down to the parallel rate. However, SerDes which do not transmit a clock use reference clock to lock the PLL to the correct Tx frequency, avoiding low harmonic frequencies present in the data stream. The receive clock may have been recovered from the data by the serial clock recovery technique. The SIPO (Serial Input, Parallel Output) block typically has a receive clock output, a set of data output lines and output data latches.
Implementations may also make use of a double-buffered register to avoid metastability when transferring data between clock domains.
The simplest form of the PISO has a single shift register that receives the parallel data once per parallel clock, and shifts it out at the higher serial clock rate. It may use an internal or external phase-locked loop (PLL) to multiply the incoming parallel clock up to the serial frequency. The PISO (Parallel Input, Serial Output) block typically has a parallel clock input, a set of data input lines, and input data latches. There are 4 different SerDes architectures: (1) Parallel clock SerDes, (2) Embedded clock SerDes, (3) 8b/10b SerDes, (4) Bit interleaved SerDes. The next stage then concatenates that single element with the list of X size coming in on the bus from the left.The basic SerDes function is made up of two functional blocks: the Parallel In Serial Out (PISO) block (aka Parallel-to-Serial converter) and the Serial In Parallel Out (SIPO) block (aka Serial-to-Parallel converter).
The nodes store an input byte in the state, converts it to a single element array in the state which holds a pointer to that byte, turns that into a single element list of a pointer to byte and emits that. There is a variadic parallel to serial input that takes in bytes and emits a custom “self” type which is the internal “List” type.
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